The present invention relates to a metal-oxide-semiconductor (MOS) device suitable for high degree of integration. In accordance with improvements in the integration degree of MOS LSI, the channel length of the MOS FET is continually made shorter. Shortening the channel length leads to an improved switching speed, but produces the following probelms.
First of all, the so-called "short channel effect", i.e., gate threshold voltage is rapidly decreased if the channel length is smaller than a certain level, must be considered. FIG. 1, shows the relationship between the channel length and the gate threshold voltage. As seen from FIG. 1, only a small change in the channel length brings about a large change in the gate threshold voltage in short channel regions. Specifically, if the channel region is short, the influence of the depletion layer formed near the source and drain regions is considerable, resulting in a decreased gate threshold voltage. In general, the potential of the substrate in which the channel region is formed is equal or very close to that of the source region. Thus, the electric field between the source and drain regions is concentrated in the surface region of the channel near the drain region and, thus, is most intensified in the surface region. It follows that the depletion layer near the drain region imparts the greatest influence in the decrease of the gate threshold voltage.
A second problem to be noted is that, if the voltage applied between the source and drain electrodes is constant, a shortened channel length results in an intensified electric field in the channel region. This enhances the probability of impact ionization caused by the channel current. It should be noted that part of the electrons or holes generated by the impact ionization bounce over the energy gap between the semiconductor substrate and the gate insulation film and flow into the gate electrode, thereby producing a gate current. In some cases, the electrons or holes bouncing over the energy gap are trapped by the gate insulation film and cannot come out of the insulation film. In this case, the device characteristics such as the gate threshold voltage and the channel conductance are permanently changed, resulting in low reliability of the device.
FIG. 2 shows a prior art MOS FET designed to prevent the electric field from being intensified near the drain region, thereby solving the problems described above. It can be seen that an n.sup.+ -type layer 12 acting as the source region of an n-channel MOS FET and n.sup.+ -type regions 14, 16 collectively forming the drain region of the n-channel MOS FET are formed in the surface region of a p-type semiconductor substrate 10. The n.sup.+ -type layer 14, which is connected to a drain electrode 28, has a relatively high impurity concentration, i.e., about 1.times.10.sup.19 /cm.sup.3, which is substantially equal to the impurity concentration of the source region 12. On the other hand, the n.sup.+ -layer 16 on the channel side has a relatively low impurity concentration, i.e., about 1.times.10.sup.17 /cm.sup.3. A gate insulation film 18 is formed on the channel region, and a gate electrode 20 is formed on the gate insulation film 18. The MOS FET further comprises a field insulation film 22, an insulation film 24 and a source electrode 26.
In the construction shown in FIG. 2, part of the voltage applied between the source and drain electrodes is applied to the low impurity portion, i.e., the n.sup.+ -layer 16, of the drain region, with the result that it is possible to weaken the electric field concentrated in the channel region near the drain region in the conventional device. It follows that it is possible to prevent the changes in the gate threshold voltage, channel conductance, etc. However, the drain region contacting the channel region, i.e., the n.sup.+ -layer 16, has a high resistance because the impurity concentration is low. The high resistance mentioned leads to a low switching speed. Further, at least one additional masking is required compared with the ordinary method to produce a drain region with a high impurity layer and a low impurity layer, leading to a complex manufacturing process for the device.